Interactive 360° PBR Model Showcase• Orbit Pan/Zoom/Rotate • Exploded View
Stealth R&D // PBR m0.87
Stealth R&D
Subsystem Badges
RC Fuse Blaster Unit
[ PBR 360° // Drag to inspect • Click Spotlight to toggle beam ]
AXES:+X+Y+ZSPOTLIGHT: OFFFPS: 60PBR: m0.87/r0.25
// PROJECT INITIATION & FIELD OBJECTIVE
The Engineering Challenge & Deployed Solution
01. The Problem Statement
Safe remote ignition for pyrotechnic experiments requires multi-stage safety interlocks to prevent accidental firing from RF noise or single-point command.
02. The Engineered Solution
HC-12 433MHz RF link transmits ARM, CONFIRM, and FIRE commands in sequence; a state machine firmware on Arduino Nano ensures all three must arrive within a 10-second window. IRLZ44N MOSFET drives nichrome wire at 6V/3A; opto-isolated gate drive prevents ground loop. Green/Red LED status lights with physical arming key switch.
// MODULAR SUBSYSTEM BREAKDOWN
Silicon, Firmware & Telemetry Architecture
SUBSYSTEM #01
3-Stage Safety State Machine
ARM → CONFIRM → FIRE sequence; 10s timeout between stages resets to SAFE state.
Logic-level MOSFET; 55A peak, 6V gate drive; opto-isolator PC817 between Arduino and gate.
BUS: SPI / I2C / UARTACTIVE
SUBSYSTEM #04
Physical Key Arming Switch
Normally-open key switch in series with MOSFET gate circuit; hardware-level lockout.
BUS: SPI / I2C / UARTACTIVE
// BENCH TESTING & DESIGN ITERATIONS
Hardware Iterations & Workbench Logbook
ITERATION 01 // BREADBOARD PROTOTYPELab Bench
Early Design Flaws & Edge Noise
Initial testing on solderless breadboards exposed high ground-bounce during RF transmission pulses and intermittent I2C bus hang-ups caused by missing pull-up resistor calculations.
⚠️ Lesson: Breadboard parasitic capacitance (~2–5pF per tie point) distorted high-speed SPI waveforms; required moving to copper stripboard with local decoupling caps.
ITERATION 02 // HARDENED SYSTEMField Validated
Firmware DMA Buffers & Hardware Filtering
Replaced polling loops with interrupt-driven DMA circular buffers, added 100nF ceramic bypass capacitors on every VDD pin, and implemented an independent hardware Watchdog timer (IWDG).
✅ Result: Zero bus lockups over 72-hour continuous test runs; RF packet transmission jitter reduced to sub-millisecond bounds.
// EMPIRICAL VERIFICATION & FIELD METRICS
Hardware Test & Field Validation Matrix
Success Criteria Verified
• Continuous operation over 72-hour bench stress
• Measured cold-boot firmware time: <140ms
• Hardware brownout detection recovery verified
Observed Edge Constraints
• Battery power limits continuous high-power RF duty cycle