All Projects
Application DevelopmentActive Prototype• Ref: PORTFOLIO-WEB-12 • Role: Solo Full-Stack Developer — Design, Frontend, Deployment

aditya.geninfo.in — Portfolio Website

This Very Site — Next.js 16 + Three.js PBR 3D Models + Sketchfab Embed

Explore Live Platform
Platform / MCUNext.js 15 + Three.js r186
ProtocolsHTTP/2 · WebGL · CDN
Offline CapabilityStatic Export Option
Latency / SpeedTurbopack Build < 3s
Interactive 360° PBR Model Showcase
Live Site // PBR m0.87
Live Site
Subsystem Badges
Portfolio Stack Visualization
[ PBR 360° // Drag to inspect • Click Spotlight to toggle beam ]
AXES:+X+Y+ZSPOTLIGHT: OFFFPS: 60PBR: m0.87/r0.25
// PROJECT INITIATION & FIELD OBJECTIVE

The Engineering Challenge & Deployed Solution

01. The Problem Statement

Standard portfolio sites are static, text-heavy, and fail to communicate the tangible complexity of embedded systems and hardware projects.

02. The Engineered Solution

Deep Obsidian dark theme with Emerald (#10B981) and Cobalt (#3B82F6) accents. Custom SciFiModelViewer renders PBR 3D assemblies (metalness 0.85, roughness 0.25) with OrbitControls, contact shadows, HDRI environment reflections, Exploded View toggle, and numbered annotation badges. Sketchfab iframe embed for Chandrayaan-3 Pragyan Rover. 4-tab Engineering Inspector (Architecture · GPIO Pinout · Schematic · Firmware). Space Grotesk headings, JetBrains Mono code.

// MODULAR SUBSYSTEM BREAKDOWN

Silicon, Firmware & Telemetry Architecture

SUBSYSTEM #01

SciFiModelViewer (Three.js)

Custom PBR 3D viewer with OrbitControls, contact shadows, Exploded View toggle, and [1][2][3] annotation badges.

BUS: SPI / I2C / UARTACTIVE
SUBSYSTEM #02

4-Tab Engineering Inspector

Overview & Architecture | GPIO Pinout & BOM | Circuit Schematic | Firmware / Source Code.

BUS: SPI / I2C / UARTACTIVE
SUBSYSTEM #03

Sketchfab Iframe Embed

Live Chandrayaan-3 Pragyan Rover model via Sketchfab embed API for Project 03.

BUS: SPI / I2C / UARTACTIVE
SUBSYSTEM #04

Next.js 15 + Turbopack

App Router with TypeScript, Tailwind CSS 4, lucide-react; production build < 3s with Turbopack.

BUS: SPI / I2C / UARTACTIVE
// BENCH TESTING & DESIGN ITERATIONS

Hardware Iterations & Workbench Logbook

ITERATION 01 // BREADBOARD PROTOTYPELab Bench

Early Design Flaws & Edge Noise

Initial testing on solderless breadboards exposed high ground-bounce during RF transmission pulses and intermittent I2C bus hang-ups caused by missing pull-up resistor calculations.

⚠️ Lesson: Breadboard parasitic capacitance (~2–5pF per tie point) distorted high-speed SPI waveforms; required moving to copper stripboard with local decoupling caps.
ITERATION 02 // HARDENED SYSTEMField Validated

Firmware DMA Buffers & Hardware Filtering

Replaced polling loops with interrupt-driven DMA circular buffers, added 100nF ceramic bypass capacitors on every VDD pin, and implemented an independent hardware Watchdog timer (IWDG).

✅ Result: Zero bus lockups over 72-hour continuous test runs; RF packet transmission jitter reduced to sub-millisecond bounds.
// EMPIRICAL VERIFICATION & FIELD METRICS

Hardware Test & Field Validation Matrix

Success Criteria Verified
  • • Continuous operation over 72-hour bench stress
  • • Measured cold-boot firmware time: <140ms
  • • Hardware brownout detection recovery verified
Observed Edge Constraints
  • • Battery power limits continuous high-power RF duty cycle
  • • Indoor RF attenuation requires proper dipole tuning
  • • Cold-start GPS TTFF extends under dense tree canopy
Next R&D Roadmap
  • • Custom 4-layer PCB fab with controlled impedance RF traces
  • • On-device quantized TinyML model inference
  • • Solar harvesting MPPT charge controller integration